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| Careers at Focus |
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ASIC DESIGN ENGINEER |
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RTL (Register Transfer Logic) design using Verilog language; SoC (System-on-Chip) architecture design for UWB (Ultra-Wideband) WiMedia MAC layer; functional Verification using Vera, C & Assembly languages; chip-level timing constraints & static timing analysis using Synopsys’Prime Time tool; post-Silicon validation. |
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Mail resumes to Focus Enhancements, Inc., Attn: Michael Ngo, 22867 NW Bennett Rd., Ste 200, Hillsboro, OR 97124 |
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ASIC DESIGN ENGINEER |
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Development of next generation Ultra-Wide-Band (UWB) wireless chip-set; participation in the architecture-design, architecture-modeling, & implementation of the UWB Physical Layer which complies to MultiBand OFDM (Orthogonal Frequency Division Multiplexing) Alliance standard. Requires architecture and implementation expertise in complex Multi-Band OFDM design; Design experience with complex SoC implementation using Verilog & Vera languages; RTL design & design verifications using ASIC mixed signal techniques; static timing analysis, using synthesis design flow techniques & scripting languages; development of golden models using Matlab languages; board level design & silicon validation. |
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Mail resumes to Focus Enhancements, Inc., Attn: Michael Ngo, 22867 NW Bennett Rd., Ste 200, Hillsboro, OR 97124 |
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WIRELESS SYSTEMS/DSP ENGINEER |
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Focus Enhancements, Inc. is looking for an energetic and experienced professional systems engineer to support the architectural design, behavioral simulation and verification support of our proprietary high data rate UWB PHY. CLICK FOR MORE DETAILS. |
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Please submit your resume to: orjobsjs@focusinfo.com. |
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RTL DESIGNER |
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ASIC Design for Digital Video SOC |
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Our Hillsboro, Oregon office is seeking a candidate to join a dynamic design team that is involved in every aspect of Digital chip design process including RTL design and verification. The duties include Video DSP algorithm development, micro-architecture development, RTL design, functional verification, Verilog/VHDL, Synthesis, Timing analysis/verification, Silicon debug. The incumbent should be a team player and should possess good communication skills (both oral and written in English). Candidates with exposure to Video Processor chip design (detailed knowledge in scaling, filtering, compression/decompression, dithering, deinterlacing, TV standards) and Mixed-Signal design will be a definite plus. Hands-on use of Logic Analyzers and Scopes are desirable. CLICK FOR MORE DETAILS. |
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Please submit your resume to: orjobskp@focusinfo.com. |
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